1. Field
Embodiments of the present invention relate to a nonvolatile semiconductor memory device.
2. Description of the Related Art
Along with miniaturization of NAND type flash memory, advances are being made in the study, commercial realization, and so on, of a memory cell of planar surface structure including a charge storage layer of a floating gate, or the like, thinned to 5 nm or less. However, because it is difficult in such a case to short-circuit only the control gate and the charge storage layer, consideration is being given to also configuring the select gate by a transistor having a structure including a charge storage layer similarly to the memory cell. Generally, when a similar structure is adopted for the select gate and the memory cell, it is often the case that the flash memory is provided with a write/erase function to the select gate and a threshold voltage of the select gate set. However, along with miniaturization of the flash memory, variation in the threshold voltage of the select gate after write also increases. In this case, it is easy for excessive write, deficient write, or the like, to occur, depending on a NAND cell unit, whereby reliability of the flash memory is impaired.